![]() ![]() Design benchmarking to 7 nm with FinFET predictive technology models. Sinha, S., Cline, B., Yeric, G., Chandra, V. Electron beam lithography in nanoscale fabrication: recent development. Realization of room-temperature phonon-limited carrier transport in monolayer MoS 2 by dielectric and carrier screening. Two-dimensional materials for next-generation computing technologies. Graphene-contacted ultrashort channel monolayer MoS 2 transistors. Direct measurement of the dielectric constants of silicon and germanium. How good can monolayer MoS 2 transistors be? Nano Lett. A 10 nm short channel MoS 2 transistor without the resolution requirement of photolithography. In 2014 IEEE International Electron Devices Meeting (IEDM) 5.3.1–5.3.4 (IEEE, 2014). Atomically thin graphene plane electrode for 3D RRAM. Metal oxide-resistive memory using graphene-edge electrodes. Lee, S., Sohn, J., Jiang, Z., Chen, H.-Y. Large-scale pattern growth of graphene films for stretchable transparent electrodes. Black phosphorus junctions and their electrical and optoelectronic applications. Electric field effect in atomically thin carbon films. Experimental demonstration of ultrashort-channel (3 nm) junctionless FETs utilizing atomically sharp V-grooves on SOI. ![]() Migita, S., Morita, Y., Matsukawa, T., Masahara, M. Integrated nanoelectronics for the future. Cramming more components onto integrated circuits. MoS 2 transistors with 1-nanometer gate lengths. Radisavljevic, B., Radenovic, A., Brivio, J., Giacometti, V. Graphene and two-dimensional materials for silicon technology. Two-dimensional semiconductors for transistors. Promises and prospects of two-dimensional transistors. It does not store any personal data.Liu, Y. The cookie is set by the GDPR Cookie Consent plugin and is used to store whether or not user has consented to the use of cookies. The cookie is used to store the user consent for the cookies in the category "Performance". This cookie is set by GDPR Cookie Consent plugin. The cookie is used to store the user consent for the cookies in the category "Other. The cookies is used to store the user consent for the cookies in the category "Necessary". The cookie is set by GDPR cookie consent to record the user consent for the cookies in the category "Functional". The cookie is used to store the user consent for the cookies in the category "Analytics". ![]() These cookies ensure basic functionalities and security features of the website, anonymously. Necessary cookies are absolutely essential for the website to function properly. “This is as far as I can rationalize it,” the Intel manager said. But it's unclear if silicon will remain a viable technology beyond the next decade. The company will continue to embrace silicon until the end of the decade. The challenge is to make devices smaller, faster, and with lower power,” he said. “Developing smaller and faster devices is not a problem. The challenge is to make devices with low “standby currents and standby power,” he said. Moore–which says the number of transistors in integrated circuits doubles every 18 months due to device shrinks and other chip-processing technologies.īefore the end of this decade–or sooner–Intel and other chip makers will face some major challenges to develop ICs with bulk silicon, especially in terms of power consumption, Marcyk said. The Intel manager was referring to the popular axiom in the semiconductor business–attributed to Intel co-founder Gordon E. “This technology will take us out at least until the end of the decade,” he said in an interview with SBN. “If you look at Moore's Law, we are trying to shrink the transistor 30% every two years,” Marcyk said. ![]()
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